Pulse-width control circuits generate an output clock signal having a desired pulse width. For example, half-rate or double-sampling data interfaces typically include a pulse-width control circuit to adjust the duty cycle of a clock signal used to sample data for transmission or reception. Similarly, programmable-duty-cycle clock systems will also include a pulse-width control circuit. To provide the desired pulse width for a clock signal, a digital approach and also an analog approach have been used in pulse-width control circuits. In the digital approach, the architecture varies whether the output clock signal is relatively high speed or low speed but both approaches involve the use of a charge pump and loop filter in a feedback loop analogous to a phase-locked loop. For example, in the low speed digital architecture, an input clock drives a delay line through a pseudo-inverter. The delay line drives a first charge pump that in turn charges/discharges a first capacitor. A reference clock pulse drives a second charge pump that also charges (or discharges) a second capacitor. An amplifier amplifies a difference between the voltages across the two capacitors that is feedback through a loop filter to adjust the pseudo-inverter such that the output of the delay has the desired pulse width. But such a digital architecture cannot achieve an arbitrary duty cycle, has limited resolution, and consumes substantial power.
In an analog approach, the architecture for the pulse-width control circuit also tend to vary depending on the clock speed. For example, one low-speed analog approach involves the use of a digital-to-analog converter to convert a digital code into an analog voltage representing the desired pulse width. An amplifier compares the analog voltage to a feedback voltage derived from the output clock signal as filtered through a low pass filter. The amplifier controls a delay line responsive to the feedback to convert an input clock signal into the duty-cycle-adjusted output clock signal. But such analog approaches also consume substantial power and have difficulty providing an arbitrary pulse width due to process, voltage, and temperature variations.
Accordingly, there is a need in the art for an improved adjustable pulse-width control circuit that is low power and calibrated against process variations and circuit non-linearities.